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HD49801FB
Digital Signal Processing IC for CCD Cameras
Preliminary
Description
The HD49801FB is an IC that integrates all the functions re q u i red for CCD camera signal processing (except the CDS and AGC blocks) in a single chip. * * Allows microprocessor control (over a serial interface) of all image quality controls. Handles all fo rm ats; NTSC, PAL, SECAM ( h oweve r, does not include a SECAM encoder). Handles 510H/760H CCD image sensors.
Features
* Generates high quality chroma and luminance signals using three-line mat rix pro c e s s i n g supported by a built-in line memory (1H x 2).
*
1
HD49801FB
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 Pin Name PLLPO PLLNO VRI CBLKO CSYNCO VDO FVO BFO IDO Signal PLL posi out PLL nega out Vertical reset in Composite blanking out Composite SYNC out Vertical driving out Field vertical out Burst flag out Line ID out I/O O O I O O O O O O
HD49801FB
Function Description In PAL/SECAM modes, the fsc and fH gen lock phase detection output External reset input for the vertical synchronization signal; high = reset Composite horizontal and vertical blanking signal Composite horizontal and vertical synchronization and blanking signal Vertical synchronization signal Field vertical synchronization signal Burst flag output Line ID PAL: High = (R-Y) +, low = (R-Y) - SECAM: High = B-Y, low = R-Y SSG (SYNC signal generator) ground 4fsc output PAD VSS 4fsc oscillator circuit input (NTSC: 4fsc = 14.31818 MHz) 4fsc oscillator circuit output (PAL/SECAM: 4fsc = 17.734475 MHz) fsc output Clock output for chroma signal (C) D/A converter; frequency = 4fsc Chroma signal (C) output (Data format: offset binary)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SSG VSS FF SCO PAD VSS X4FSCI X4FSCO SCO CCK CO (8) CO (7) CO (6) CO (5) CO (4) CO (3) CO (2) CO (1) TEST1 YCK YO (8) YO (7) YO (6) YO (5) YO (4) YO (3) YO (2) YO (1)
VSS for SSG 4fsc out VSS for PAD 4fsc osc in 4fsc osc out Sub carrier out C clock for DAC Chroma out (8): MSB Chroma out (7) Chroma out (6) Chroma out (5) Chroma out (4) Chroma out (3) Chroma out (2) Chroma out (1): LSB Test 1 Y clock for DAC Y out (8): MSB Y out (7) Y out (6) Y out (5) Y out (4) Y out (3) Y out (2) Y out (1): LSB
VSS O VSS osc osc O O O O O O O O O O I O O O O O O O O O
Test pin: Fix at the low level Clock output for luminance signal (Y) D/A converter; frequency = 4fsc Luminance signal (Y) output
2
HD49801FB
Pin Functions (cont)
Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Pin Name YPO (8) YPO (7) YPO (6) Signal Y pararell out (8): MSB Y pararell out (7) Y pararell out (6) I/O O O O VDD O O O O O I I I I I I I I O O O O I I I I O Y digital interface input VDD for core, VDD = 5 V +0.25 V
-0.50 V
HD49801FB
Function Description Y digital interface output Outputs the post-gamma compensation Y signal
CORE VDD VDD for core YPO (5) YPO (4) YPO (3) YPO (2) YPO (1) YPI (8) YPI (7) YPI (6) YPI (5) YPI (4) YPI (3) YPI (2) YPI (1) CPO (4) CPO (3) CPO (2) CPO (1) CPI (4) CPI (3) CPI (2) CPI (1) NRYBYO DICKO HREFI Y pararell out (5) Y pararell out (4) Y pararell out (3) Y pararell out (2) Y pararell out (1): LSB Y pararell in (8): MSB Y pararell in (7) Y pararell in (6) Y pararell in (5) Y pararell in (4) Y pararell in (3) Y pararell in (2) Y pararell in (1): LSB C pararell out (4): MSB C pararell out (3) C pararell out (2) C pararell out (1): LSB C pararell in (4): MSB C pararell in (3) C pararell in (2) C pararell in (1): LSB R-Y, B-Y phase out
Y digital interface output
C digital interface output (data format: two's complement) Color difference signals R-Y and B-Y Upper to lower order C digital interface input (data format: two's complement)
C digital interface phase output; high = (B-Y) phase, low = (R-Y) phase Digital interface clock output, frequency = fs VSS for core Horizontal scan reference signal Reference for memory start/stop, BF, CBLK, and CSYNC Line signals (two types) determination input; high = a, b; low = c, d (state data A7) Sensor clock (system clock) fs input A/D input
Digital interface clock out O VSS I Horizontal reference in
CORE VSS VSS for core
64 65 66 67 68
HGI SCKI ADI (9) ADI (8) ADI (7)
Horizontal gate in Sensor clock in AD in (9): MSB AD in (8) AD in (7)
I I I I I
3
HD49801FB
Pin Functions (cont)
Pin No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name ADI (6) ADI (5) ADI (4) ADI (3) ADI (2) ADI (1) ADI (0) OBPI CPREFO KNEEO EP3O EP2O EP1O TBI TGI TRI TKEYI NMEI IWNI PAD VDD DETLDI DETCKI DETSO SLDI STCKI SDI IDSI CHDO SSG VDD XHCKI XHCKO Signal AD in (6) AD in (5) AD in (4) AD in (3) AD in (2) AD in (1): LSB AD in (0) Optical black pulse in Clamp reference out Knee point out Iris V edge pulse 3 out Iris V edge pulse 2 out Iris V edge pulse 1 out Titler B in Titler G in Titler R in Titler key in Memory enable bar in Iris/white balance in VDD for PAD DET load in DET clock in DET serial out State load in State clock in State data in Line ID reset in Camera HD out VDD for SSG H osc in H osc out I/O I I I I I I I I O O O O O I I I I I I VDD I I O I I I I O O VDD osc osc Fix at the low level Function Description A/D input
HD49801FB
Sensor optical black period input; high during the OB period Feedback clamp OBP detection output (0 V to 5 V) Knee point setting output; high = iris region 6 V direction iris setting region Iris V-window pulse 3 output Iris V-window pulse 2 Iris V-window pulse 1 Title color setting signal
Title on/off signal; high = on, low = off Line memory R/W enable signal; high = disable, low = enable DETSO function selection (iris/WB) input; high = iris, low = WB VDD for pad, VDD = 5 V Iris/WB load pulse Iris/WB clock pulse Iris: Average value (22b)/peak value (11b) WB: Mg-G (11b), R-B (11b) Image quality control data (state data) load pulse Image quality control data (state data) clock pulse Image quality control data (state data) input In PAL/SECAM mode, line ID reset input; high = reset TG CSYNC output Camera horizontal synchronization output VDD for SSG, VDD = 5 V
+0.25 V -0.50 V +0.25 V -0.50 V
TGSYNCO TG sync out
H oscillator input (NTSC: 260 fH = 4.090908 MHz) H oscillator output (PAL/SECAM: 282 fH = 4.40625 MHz)
4
HD49801FB
Block Diagram
CO CCK YO YCK
HD49801FB
8 A9 C-Y C-YW gain gain A6 C-Y matrix compensation RGB gain + RGB set up A5 compensation A8
8
(D1 to D18) (A1 to A16)
State data interface
Modulator
SDI STCKI SLDI
Title fade inversion
Titler in
TBI TGI TRI TKEYI 4 4 8 8 CPI CPO YPI YPO NRYBYO DICKO
A5
A4
Digital interface
A12 A1 to A3 RGB matrix + W/B detection A10 Y setup Iris detection A13 H clip, enhancer H Y filter V + A15 1HDL 1HDL Control Internal TG A14 (fs block) SSG (4fsc block) IDO BFO CSYNCO CBLKO TGSYNCO CHDO VDO FVO V clip, enhancer EP1O EP2O EP3O KNEEO DETSO Iris/WB interface DETLDI DETCKI IWNI
A7
C clip level
Color distribution C filter 1 C filter 2
A11
OBP detect 9 ADII-9 NMEI CPREFO OBPI HREFI HGI SCKI
TESTI
X4FSCI X4FSCO FFSCO SCO HOSCI HOSCO PLLPO PLLNO VRI IDSI
33 VDD V SS ADI0
Note: A1 to A15 indicate state data.
5
HD49801FB
Standard External Circuits
HD49801FB
Y interface inputs
Y interface outputs
Y interface outputs
Y signal outputs
Y DAC clock output
+ -
100 F/6.3 V
Y interface input
C interface inputs
C interface outputs C digital interface phase output Digital interface clock output Synchronization pulse inputs
A/D inputs
OBP input Units: R: C: F L: H
6
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Color signal outputs
1 M
HD49801FB
CDAC clock output fsc output 15 pF X'tal 14.31818 MHz 25 pF 4fsc output
Synchronization pulse outputs
Iris pulse output + - 10 F/ 6.3 V 5V
Iris/WB control pulse inputs 47 F DET SO selection
Image quality control pulse outputs
Synchronization pulse outputs
DET SO
+ 100 F/ 6.3 V
0.1 F
NTSC Standard External Circuits
HD49801FB
Standard External Circuits (cont)
Y DAC clock output
HD49801FB
Y interface inputs
Y interface outputs
Y interface outputs
Y signal outputs
+ -
100 F/6.3 V
Y interface input
C interface inputs
C interface outputs C digital interface phase output Digital interface clock output Synchronization pulse inputs
A/D inputs
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Color signal outputs
HD49801FB
CDAC clock output fsc output 1 M 15 pF X'tal 17.73 MHz 25 pF 4fsc output
Synchronization pulse outputs
Iris pulse output + - 10 F/ 6.3 V OBP input Units: R: C: F L: H 5V
Iris/WB control pulse inputs 47 F DET SO selection
Image quality control pulse outputs
Synchronization pulse outputs 1500 pF 1M
X'tal 4.406 MHz 50 pF
0.1 F 56 k
470 k 0.1 F
100 k
DET SO
+ 100 F/ 6.3 V
0.1 F
PAL Standard External Circuits
7
HD49801FB
Absolute Maximum Ratings (Ta = 25C)
Item Power supply voltage Pin voltage Pin voltage Output voltages Corresponding to one output Corresponding to one GND to VCC Operating temperature Storage temperature Symbol VCC Vti Vto Io Iot Topr Tstg Rated Value -0.3 to +6.7 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -16 to +16 -70 to +70 -10 to +75 -55 to +125
HD49801FB
Unit V V V mA mA C C
Notes: 1. This IC can be permanently damaged by operating at values in excess of its absolute maximum ratings. Furthermore, it is desirable to operate this IC within the conditions for the electrical characteristics specifications during normal operation. Exceeding those conditions can result in incorrect operation and a reduction in reliability. 2. All voltages are specified with GND = 0 V as the reference. 3. This IC is for use in consumer products. It should not be used in industrial products, or in products that will be used outdoors for extended periods.
Electrical Characteristics (VCC = 5 V -0.50V Ta = -10C to +75C)
Item Input voltages* Symbol VIHC VILC Output voltages* VOH VOL Input leakage current Output leakage current Current dissipation ILI ILO ICC Min VCC x 0.7 -- 2.4 -- -1.0 -1.0 -- Typ -- -- -- -- -- -- -- Max -- VCC x 0.3 -- 0.4 1.0 1.0 110 Unit V V V V A A mA Test Conditions CMOS levels CMOS levels IOH = 2/4 mA IOL = -2/-4 mA VIN = 0 to VCC Output high impedance state With VCC = 5 V, and no load, Ta = 25C, fCLK = 14.3 MHz
+0.25 V
Note: * I/O voltage levels are measured in steady state.
8
HD49801FB
Crystal Oscillator Circuit
* Test conditions VCC = 5 V 5% Cin, Cout = 22 pF Rf = 10 M * Test method Test at fmin = 8 MHz and fmax = 20 MHz under the above conditions. Note that the oscillator start time (tosc max) is 250 ms.
HD49801FB
To the internal oscillator
Rf Xin Xout Divider counter Cin Cout Monitor pin
Counter
Test Circuit
9
HD49801FB
Overview of Pixel Mixing CCD-RGB Simultaneous Processing
HD49801FB
G Cy Mg Cy
Mg Ye G Ye
G Cy Mg Cy
Mg Ye G Ye
G Cy Mg Cy
Mg G + Cy Ye G Ye Mg + Cy G + Ye Mg + Cy G + Ye Line (N + 1) Mg + Ye G + Cy Mg + Ye Line N
G + Cy = G + (G + B) = 2G + B = Gb Mg + Ye = (R + B) + (R + G) = (R + G + B) + R = Wr Mg + Cy = (R + B) + (G + B) = (R + G + B) + B = Wb G + Ye = G + (G + B) = 2G + R = Gr
Pixel Mixing CCD Mode Figure RGB matrix R B K Gb.r K Gb.b K Wr.r K Wr.g K Wr.b K Wb.r K Gr.r Gb Wr Wb Gr
G = K Gb.g
K Wb.g K Gr.g K Wb.b K Gr.b
Y matrix * * Line N Y = Gb + Wr = (2G + B) + (2R + G + B) = 2R + 3G + 2B Line (N + 1) Y = Wb + Gr = (R + G + 2B) + (2G + R) = 2R + 3G + 2B
10
HD49801FB
Line Signal Processing
RGB matrix Rn + 1 Gn + 1 Bn + 1 =A Gbn Wrn (Wbn - 1 + Wbn + 1)/2 (Grn - 1 + Grn + 1)/2
HD49801FB
C-Y matrix Rn + 1 =C Gn + 1 Bn + 1 = CA Gbn Wrn (Wbn - 1 + Wbn + 1)/2 (Grn - 1 + Grn + 1)/2
(R-Y)n + 1 (B-Y)n + 1
Three line signal processing Sensor output 1 HDL memory n-1 n Y processing * Enhancer * Gamma C processing * RGB matrix * Gamma, C-Y R-Y B-Y
1 HDL memory
n+1
Y
CCD Camera RGB Simultaneous Processing
11
12
Data Notes KdR Sign KcR Sign KbR Sign KaR KdG Sign KcG Sign KbG Sign KaG KdB Sign KcB Sign KbB Sign KaB B gain Exponent Mantissa G gain Exponent Mantissa R gain Exponent W/B RGB gain Mantissa: 3 bits Exponent: 8 bits Yr control control: 3 bits 8 stages (0 to 1) R-Y gain C base clip Color difference gain: 7 bits Burst level: 7 bits Burst clip: 3 bits b base clip a base clip Clip level: 9 bits c base clip Data Encoder (FAD) Data Encoder (MOD) Setup data Y, R, G, B setup H base clip V enhancer gain V base clip H enhancer noise coefficient H enhancer frequency characteristics Y enhancer base clip Data W/B detection Count value Iris detection Data (timing) H synchronization pulse timing Mode, test
State
Address
A
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48
1
0
0
0
0
R matrix coefficients Sign (11 bits x 4 channels) 10 bits + 1 sign bit D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
HD49801FB
2
State Data Table
1
0
0
0
G matrix coefficients Sign (11 bits x 4 channels) 10 bits + 1 sign bit D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
3
0
1
0
0
B matrix coefficients Sign (11 bits x 4 channels) 10 bits + 1 sign bit D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Mantissa
4
1
1
0
0
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Cr control
Cr dark clip
5
0
0
1
0
D1 D2 D3 D1 D2 D3 D1 D2 D3
B-Y gain
6
1
0
1
0
D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 D1 D2 D3
d base clip
7
0
1
1
0
D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 D2 D3 D4 D5 D6 D7 D8 D9
Address L
8
1
1
1
0
D1 D2 D3 D1 D2 D3 D4 D5 D6 D7 D8
9
Address L
0
0
0
1
D1 D2 D1 D2 D3 D4 D5 D6 D7
10
Address L
1
0
0
1
D1 D2 D1 D2 D3 D4 D5 D6 D7 D8 D9
Address H
H enhancer gain
11
0
1
0
1
D1 D2 D3 D4 D5 D1 D2 D3 D4 D1 D2 D3 D4 D5 D1 D2 D3 D4 D1 D2 D3 D4 D5 D1 D2
Address H
Address L
12
1
1
0
1
D1 D2 D3 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
Address H
Address L
13
0
0
1
1
D1 D2 D3 D4 D1 D2 D3 D4 D5
Address H
Address L
14
1
0
1
1
D1 D2 D3 D4 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
Address H
16
HD49801FB
1
1
1
1
HD49801FB
State Data Details
The following items describe the state data (A1 to A16) in detail. State Data A1 to A3: RGB matrix This data specifies color reproducibility and moire pattern suppression.
Coefficient K Gb , j Coefficient K Wr, j Coefficient K Wb, j
HD49801FB
Coefficient K Gr , j
Address
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD DD 00 1110 9 8 7 6 5 4 3 2 1 1110 9 8 7 6 5 4 3 2 1 1110 9 8 7 6 5 4 3 2 1 1110 9 8 7 6 5 4 3 2 1 21 Mantissa Exponent (j = RGB)
Address 0000 0001 0010
Matrix R G B
Gb Wr Wb Gr R G = A (Kij) B
Gb Wr Wb Gr
R G B
Kij
Kij = (-1)D11 * 2-(D10 x 2 + D9 x 2 ) * (D8 x 2-1 + D7 x 2-2 + D6 x 2-3 + D5 x 2-4 + D4 x 2-5 + D3 x 2-6 + D2 x 2-7 + D1 x 2-8)
1 0
Where: i = Gb, Wr, Wb, Gr j = R, G, B Determine the size of the coefficients so that MAX (KGbj, KWrj, KWbj, KGrj) = 255/256(00011111111). State Data A4: W/B RGB gain This data adjusts the amplitude of the color signal and determines the color reproducibility. It also adjusts the white balance for images of white objects.
R gain: GR G gain: G G B gain: GB Address
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD0 0 1 1 1110 9 8 7 6 5 4 3 2 1 1110 9 8 7 6 5 4 3 2 1 1110 9 8 7 6 5 4 3 2 1 Mantissa Exponent
Gi = 2 (D11 x 22 + D10 x 21 + D9 x 20 + 1) * (D8 x 2-1 + D7 x 2-2 + D6 x 2-3 + D5 x 2-4 + D4 x 2-5 + D3 x 2-6 + D2 x 2-7 + D1 x 2-8)
13
HD49801FB
D11 D10 D9 Max 1 0 1 D8 1 . . . 1 1 . . . 1 1 . . . 1 1 . . . 0 D7 1 . . . 0 1 . . . 0 1 . . . 0 1 . . . 0 D6 1 . . . 0 1 . . . 0 1 . . . 0 1 . . . 0 D5 1 . . . 0 1 . . . 0 1 . . . 0 1 . . . 0 D4 1 . . . 0 1 . . . 0 1 . . . 0 1 . . . 0 D3 1 . . . 0 1 . . . 0 1 . . . 0 1 . . . 0 D2 1 . . . 0 1 . . . 0 1 . . . 0 1 . . . 0 D1 1 . . . 0 1 . . . 0 1 . . . 0 1 . . . 0 Gi
HD49801FB
26 x 255/256 . . . 26 x 128/256 25 x 255/256 . . . 25 x 128/256 22 x 255/256 . . . 2 x 128/256 2 255/256 . . . 0
1
0
0
0
0
1
0 Min
0
0
*
Setting the gains -- Set up the RGB matrix. -- Adjust the black level for the above matrix. -- Hold G R and G B at 0, and increase GG. Determine the gain at which the output signal is saturated, and take half of that gain to be the rated gain. -- Determine GR and GB for the gain GG determined above.
14
HD49801FB
State Data A5: characteristics
HD49801FB
One of eight different curves can be selected for the characteristics by specifying the value (0 to 7) of this state data item.
(output) 256 192 128 64
0123 4 5
6 7
0
256
512
768
1023 (input)
(1) Y- I/O characteristics (state data values 0 to 7) (output)
255 192 128 64 0 0
7
512
1023 (input)
(2) C- I/O characteristics (state data values 0 to 7) (output) (output)
64 7 1 a
64
6
a
0
0
128
256 (input)
0
128
256 (input)
(3) CL- I/O characteristics (state data values 0, 2, 4, and 6) C- state data value 0 (shifted by only the amount a from the output level of (2))
(4) CL- I/O characteristics (state data values 1, 3, 5, and 7) C- state data value 0 (shifted by only the amount a from the output level of (2)) 15
HD49801FB
State Data A6: Color difference gain, base clip This data determines the signal levels of the color difference signals.
C clip CLC R-Y gain G R-Y R-Y gain G R-Y 0
HD49801FB
Address 1 0 1
D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1
*
Color difference gain control characteristics
R-Y - 127 128 to + 256 256
8
-CL C +CL C Base clip
GR-Y
x
Out In
8
(R-Y)'
B-Y - 127 128 to + 256 256
8
-CL C +CL C
GB-Y
x
8
(B-Y)'
0 to CL C
7 256
GR-Y, GB-Y = D7 x 20 + D6 x 2-1 + D5 x 2-2 + D4 x 2-3 + D3 x 2-4 + D2 x 2-5 + D1 x 2-6 (0 to 2) * Base clip level control characteristics CLC max = 7/256 = 0.0273437 CLC = D3 x 2-6 + D2 x 2-7 + D1 x 2-8 * Setting the gains (a) The ratio of the gains R-Y and B-Y is determined by the color reproduction. (b) Increase the color difference gain from the gain ratio from item (a) above. (c) Set the gain to have a 10% to 20% margin from the gain at the point the output signal clips in item (b) above. I.e., (set gain) = (clipping gain) x 0.8 to 0.9
16
HD49801FB
State Data A7: C clip level
HD49801FB
This data varies the clip levels for the complementary color signals Wr, Wb, Gr, and Gb, and determines the color reproduction.
HGI pin For example: (Wrn Gbn Grn Wbn) an bn cn dn an + 1 bn + 1 cn + 1 dn + 1
Sn From the line delay
C filter 1 C filter 2
Limiter Color distribution Out
Sn - 1 + Sn + 1 2 a level b level c level d level
Address data
A7 state
MPX
Clip a b c d a b c d
Data
Address
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2019181716151413121110 9 8 7 6 5 4 3 2 1 a clip level b clip level c clip level d clip level
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 0110 987654321987654321987654321987654321
*
Setting the clip levels -- When saturation occurs within the ADC D range: Let A be the level of a saturated pixel, and taking the white light signal levels to be Wa, Wb, Wc, and Wd, (clip level) = A x Wi/Wmax (Wmax = max {Wi}, i = a, b, c, d) -- When saturation occurs above the ADC D range: White light signal levels to be Wa, Wb, Wc, and Wd, (clip level) = 511/512 x Wi/Wmax (Wmax = max {Wi}, i = a, b, c, d)
17
HD49801FB
State Data A8 (1 to 3): Encoder (FADE) This data determines the fade level for the luminance and chroma signals.
Address H Address Data
HD49801FB
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Y fade 1 1 1 1 0 0 0 0 D1 D2 D3 D4 D5 D6 D7 D8 C fade 2 1 1 1 0 1 0 0 D1 D2 D3 D4 D5 D6 D7 D8 C inversion D1 D2
Y inversion 3 1 1 1 0 0 1 0
1: Y fade D8 = 1: Through When D8 = 0, the following weighting formula is used. D7 x 2-1 + D6 x 2-2 + D5 x 2-3 + D4 x 2-4 + D3 x 2-5 + D2 x 2-6 D1 is fixed at 0. Note: However, since the encoder fade precision is inadequate, improved fading characteristics can be obtained by using the iris function for Y fading. 2: C fade D8 x 20 + D7 x 2-1 + D6 x 2-2 + D5 x 2-3 + D4 x 2-4 + D3 x 2-5 + D2 x 2-6 + D1 x 2-7 Range: 1 to 255/128 3: Y and C inversion D1 = 0; D2 = 0: Normal D1 = 1; D2 = 1: Inversion
18
HD49801FB
State Data A9: 1 to 4 (MOD)
HD49801FB
Determines the luminance signal black level and the chroma signal burst level. These four data items determine the (R-Y) burst level for PAL format TV signals.
Address H Address Data
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 BLK level 1 0 0 0 1 0 0 D1 D2 D3 D4 D5 D6 D7 D8 Pedestal * 2 0 0 0 1 1 0 D1 D2 D3 D4 D5 D6 D7 D1 Burst level (B-Y) 3 0 0 0 1 0 1 D1 D2 D3 D4 D5 D6 D7 Burst level (R-Y) 4 0 0 0 1 1 1 D1 D2 D3 D4 D5 D6 D7
Note: Set D1 according to the delay sensor clock as follows. 14.3 MHz: D1 = 1 9.5 MHz: D1 = 0
*
State data A9 (1 to 4): Encoder (MOD) control characteristics
1: Setup (D7 x 26 + D6 x 25 + D5 x 24 + D4 x 23 + D3 x 22 + D2 x 21 + D1) x 2/256 2: Pedestal D7 x 26 + D6 x 25 + D5 x 24 + D4 x 23 + D3 x 22 + D2 x 21 + D1/256 Note: However, when the A9 to A2 D8 bit (delay) is set to 1, the Y data is delayed by one fs clock cycle. 3: Burst level (B-Y) D7 x 26 + D6 x 25 + D5 x 24 + D4 x 23 + D3 x 22 + D2 x 21 + D1/256 4: Burst level (R-Y) * Used in PAL mode * In NTSC mode, used for phase adjustment
256 . . . . . . . . B. . . . . . . . . . 0
Rating A 192
Pedestal Display period BLK level
Output D range (B/A) x 100% The D range can be set by changing the pedestal and BLK levels.
19
HD49801FB
State Data A10 (1 to 4): Y, R, G, B setup
HD49801FB
This data determines the black color when black objects are imaged, and the color reproduction.
Address H Address Data
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Y setup 1 1 0 0 1 0 0 D1 D2 D3 D4 D5 D6 D7 B setup 2 1 0 0 1 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 G setup 3 1 0 0 1 0 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 R setup 4 1 0 0 1 1 1 D1 D2 D3 D4 D5 D6 D7 D8 D9
*
State data A10: Y, R, G, B setup
1: Y setup D7 x 2-4 + D6 x 2-5 + D5 x 2-6 + D4 x 2-7 + D3 x 2-8 + D2 x 2-9 + D1 x 2-10 Note: The Y setup is the initial state Y level minus the value calculated above. 2 to 4: R, G, B setup -D9 x 2-4 + D8 x 2-5 + D7 x 2-6 + D6 x 2-7 + D5 x 2-8 + D4 x 2-9 + D3 x 2-10 + D2 x 2-11 + D1 x 2-12 Note: D9 is the sign bit. This is a two's complement value. * Notes on setup level adjustment Adjust the black level after setting the RGB matrix. The iris detection block can be used to adjust the black level. When a color difference signal is input to the iris detection block the difference with the setup target value for the specified area can be detected. Processing this detection output allows, for example, the black level to be adjusted by adjusting the R, G, B setup levels. The color difference signal is input to the iris detection block using the following method.
D1 D2 D3 D4
State data A13 to A15
Address L Data D9
0
1
1
1
High
20
HD49801FB
State Data A11: H and V enhancer This data specifies boundary compensation on video signals.
H enhancer frequency characteristics
HD49801FB
H enhancer noise coefficient: KH1
V base clip CLV
V enhancer noise coefficient: KV
H base clip CLH
H enhancer coefficient: KH2
Address 0 1 0
D2 D1 D5 D4 D3 D2 D1 D4 D3 D2 D1 D5 D4 D3 D2 D1 D4 D3 D2 D1 D5 D4 D3 D2 D1 1
Out CLH CLH KH2 In
KH1
KH1, KH2, KV = D5 x 2-1 + D4 x 2-2 + D3 x 2-3 + D2 x 2-4 + D1 x 2-5 (0 to 1) CLV, CLH = D4 x 23 + D3 x 22 + D2 x 21 + D2 x 20/1024 H Enhancer: Frequency characteristics
D2 0 0 1 1 D1 0 1 0 1 Peak Frequency 0.25 fs 0.25 fs 0.275 fs 0.3 fs
21
HD49801FB
State Data A12 (1 to 5): White balance detection
HD49801FB
This data determines the white balance detection region, sets the dead band, and determines the control range.
Address H Address Data
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 R-Y gain 1 1 1 0 1 0 0 0 B-Y gain
D1 D2 D3 D4 D1 D2 D3 D4 Y level 1 Y level 2
2
1
1
0
1
1
0
0
D1 D2 D3 D4 D1 D2 D3 D4 Offset + Offset -
3
1
1
0
1
0
1
0
D1 D2 D3 D4 D5 D6 D1 D2 D3 D4 D5 D6 C level 1 + C level 1 -
4
1
1
0
1
1
1
0
D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 C level 2 + C level 2 -
5
1
1
0
1
0
0
1
D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7
1: R-Y gain, B-Y gain These adjust the R-B/Mg-g detection axis. Gain = D4 x 2-1 + D3 x 2-2 + D2 x 2-3 + D1 x 2-4 2: Y level 1, Y level 2 When the Y signal is used as the white detection area data, the Y signal detection range is set by Y level 1 (lower bits) and Y level 2 (upper bits). The data consists of 8 bits, and the upper 4 bits (D1 to D4) can be changed. 3: Offset The control center can be shifted by setting the offset. Of the 8 bits of this data, the data that can be changed consists of 6 bits (64/256 = 1/4), and the offset level can be changed over up to 1/4 of the full data range.
22
HD49801FB
HD49801FB
4, 5: C levels This data specifies the white detection region. Of all 8 bits of this data, the data that can be changed consists of 7 bits (128/256 = 1/2), and the white detection region can be changed over up to 1/2 of the full data range. The C level data correspondences are as follows: C level 1 + The down direction of the (Mg-G) signal. C level 1 - The down direction of the (R-B) signal. C level 2 + The up direction of the (Mg-G) signal. C level 2 - The up direction of the (R-B) signal.
R-Y R-B
Mg-G Color temperature variation B-Y
(256) 94%
100%
Variable width (16 divisions)
6% (0)
0%
Y Detection Variable Width
R-Y/B-Y R, G, B gain Parallelserial conversion White detection U/D counter White detection range +/- Offset Mg-G/R-B R-Y/B-Y gain adjustment (detection axis adjustment)
Y Microprocessor
Y level detection
White Balance Detection Block Diagram
23
HD49801FB
State Data A13 (1 to 16): Iris
HD49801FB
This data determines the regions required for iris control, and selects the type of iris data to be extracted.
Address H Address Data
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 H count 1 1 0 0 1 1 0 0 0 0 D1 D2 D3 D4 D5 H count 2 2 0 0 1 1 1 0 0 0 D1 D2 D3 D4 D5 H count 3 3 0 0 1 1 0 1 0 0 D1 D2 D3 D4 D5 H count 4 4 0 0 1 1 1 1 0 0 D1 D2 D3 D4 D5 H count 5 5 0 0 1 1 0 0 1 0 D1 D2 D3 D4 D5 H count 6 6 0 0 1 1 1 0 1 0 D1 D2 D3 D4 D5
7
0
0
1
1
0
1
1
0
8
0
0
1
1
1
1
1
0 V count 1
9
0
0
1
1
0
0
0
1
D1 D2 D3 D4 D5 V count 2
10
0
0
1
1
1
0
0
1
D1 D2 D3 D4 D5 V count 3
11
0
0
1
1
0
1
0
1
D1 D2 D3 D4 D5 V count 4
12
0
0
1
1
1
1
0
1
D1 D2 D3 D4 D5 V count 5
13
0
0
1
1
0
0
1
1
D1 D2 D3 D4 D5
Peak detection region
14
0
0
1
1
1
0
1
1
D1 D2 D3 Knee
15
0
0
1
1
0
1
1
1
D1 D2 Iris region
16
0
0
1
1
1
1
1
1
D1 D2 D3
24
HD49801FB
* Iris
HD49801FB
Pattern 1 is selected if the H count 6 is in the blanking period, and pattern 2 is selected otherwise.
H count 1 1 1 2 3 4 5 3 Pattern 1 V count 2 3 4 5 2 1 2 3 4 5 3 V count 6' 1 1 3
H count 2 2 4 6 5 1'
6 5 4
6 5 4 Pattern 2 3'
The screen is divided into 6 regions -- The full integrated value (the average value of Y following processing) for each region is calculated for each field. -- Also, once for each field, the peak value for region 1 is detected. -- However, the detection region can be set to an arbitrary region (regions 1 to 6). Each region can be changed in units of 32 fs-1 horizontally, and 16 lines vertically.
State Data
D3 0 0 0 0 1 1 1
D2 0 0 1 1 0 0 1
D1 0 1 0 1 0 1 0
Region 1 2 3 4 5 6 Peak data
Note: For the peak data, the region is specified by the A13 to A14 peak detection region.
Iris control is performed with the average value acquired by adding the weighted average values for each region. Y i * ki ki
6
Y=
i=1 6
Where: Y: The average value for a single field. Yi: The average value for each region. ki: The weighting for each region.
i=1
25
HD49801FB
* The meaning and use of EP1O, EP2O, and EP3O
HD49801FB
These operate as the iris V window pulses, and output V direction edge pulses for the iris detection region.
EP1O
EP2O EP3O
26
HD49801FB
HD49801FB
State Data A14 (1 to 16): H synchronization pulse timing This data specifies both the data acquisition timing conforming to that required by the CCD sensor as well as the horizontal synchronization pulse generation.
Address H Address Data
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 Memory R/W start 1 1 0 1 1 0 0 0 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Memory R/W stop 2 1 0 1 1 1 0 0 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 H synchronization pulse 1 3 1 0 1 1 0 1 0 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 H synchronization pulse 2 4 1 0 1 1 1 1 0 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
5
1
0
1
1
0
0
1
0
6
1
0
1
1
1
0
1
0
7
1
0
1
1
0
1
1
0
8
1
0
1
1
1
1
1
0 H synchronization pulse 3
9
1
0
1
1
0
0
0
1
D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 4
10
1
0
1
1
1
0
0
1
D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 5
11
1
0
1
1
0
1
0
1
D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 6
12
1
0
1
1
1
1
0
1
D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 7
13
1
0
1
1
0
0
1
1
D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 8
14
0
0
1
1
1
0
1
1
D1 D2 D3 D4 D5 D6 D7 D8 H synchronization pulse 9
15
1
0
1
1
0
1
1
1
D1 D2 D3 D4 D5 D6 D7 D8
16
1
0
1
1
1
1
1
1 27
HD49801FB
State Data A16 (1 to 2): Mode setting
HD49801FB
This data determines the handling of the TV format, whether the digital interface is used, and the data input format.
Address H L SECAM
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 PLLON HCKC DCKC DCE PAL GE NE
1
11110
Test mode 2 11111 All 0
*
TV format
PAL 0 1 0 NTSC PAL SECAM
*
HCKC: REF and OBP latch phase 1: Positive phase (rising edge) 0: Reverse phase (falling edge)
SECAM 0 0 1
H.REF Sensor lock
*
DCKC: AD1 to AD9 latch phase 1: Positive phase (rising edge) 0: Reverse phase (falling edge)
Detected on the positive (or reverse) phase of the sensor lock signal.
*
NE 1: Does not encode 0: Does encode Note: When NE is set to 1, no encoding is performed, and the color difference signal is output from the CO pin without modulation. The HD49801FB should normally be used with NE = 0.
*
DCE: Digital interface control 1: On 0: Off
*
PLLON Set to 1 when locking externally in NTSC mode.
*
GE: Grey code enable 1: Grey code 0: Binary code
*
A2 to A16 are for use in test mode, and D6 to D28 should be set to all zeros in advance.
28
HD49801FB
State Data Transfer Timing Specifications
Image Quality Control Protocol Timing * Image quality control data (state data) transfer protocol
t WLDF SLDI STCKI t WCKL SDI Dn Dn - 1 t DS Dn - 2 t DH D1 t WCKH t WLDL
HD49801FB
Min t WLDF t WLDL t WCKH t WCKL t DS t DH 280 ns 280 ns 140 ns 140 ns 140 ns 140 ns
*
Iris, W/B data transfer protocol
tS VDO t WLD DETLDI DETCKI t WCKL DETSO Dn Dn - 1 Dn - 2 D1 t WS t WCKH
Iris D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 (average MSB value) Iris (peak) White:
Balance
D6 D5 D4 D3
D2 D1
LSB
D11 D10 D9 D8
MSB
D7 D6 D5 D4
D3 D2 D1
LSB
D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
MSB LSB MSB LSB
Mg-G (two's complement) IWNI = high: Iris selection, State data: Average/peak selection IWNI = low: White balance selection
R-B (two's complement) Min t WLD t WS t WCKH t WCKL tS 80 fs -1 2 fs -1 140 ns 140 ns 10 s
29
HD49801FB
* A/D input data (line delay memory R/W) transfer protocol
HD49801FB
HREFI Start address (state data A14 to A1) ADI1 to ADI9 SCKI State data A16 DCKC: 1: Positive phase (ADI1 to ADI9 latched on the rising edge of SCKI) 0: Reverse phase (ADI1 to ADI9 latched on the falling edge of SCKI) State data A16 HCKC: 1: Positive phase (HREFI falling edge detected on the rising edge of SCKI) 0: Reverse phase (HREFI falling edge detected on the falling edge of SCKI) D1 Stop address (state data A14 to A2) D2 D768
*
Line delay memory R/W setting example
Memory start address SCKI HREFI HREFI falling edge detection Memory stop counter clear
Memory stop address
ADI1 to ADI9 (HGI = H)
an
bn
an + 1 bn + 1
an+m bn+m
(For example, Wrn Gbn) ADI1 to ADI9 (HGI = L) cn dn cn + 1 dn + 1 cn+m dn+m
(For example, Grn Wbn) Valid data (max: 768) A14 to A1 (memory start address) A14 to A2 (memory stop address) A16 to A1 (mode): HCKC = 1, DCKC = 1
The relationship between the CCD sensor complementary color signals (Wrn, Gbn, Grn, and Wrn) and state data A7 (a, b, c, d) is determined by the relationship between the HGI input and the start address. HGI is a line determination input, and when high, the two complementary color signals correspond to (a, b), and when low, they correspond to (c, d).
30
HD49801FB
* Definition of H.REF H.REF is the standard for determining: -- Memory R/W start/stop timing -- BF, CBLK, CSYNC pulse timing * Conditions required of H.REF
HD49801FB
-- H.REF is a pulse generated from the sensor clock (fs), and must be phase stable with respect to fs. -- It must be a continuous pulse with no missing pulse periods during the BLK or other period. -- Synchronization is horizontal scan synchronization. -- tWH = Min 2 fs-1 -- Timing corresponding to the effective pixel region for the falling edge of HREFI.
Min tF tB 30 fs-1 0
However, there are no special requirements when the following relationship is met: fs = 4n * fH (where n is an integer). -- Setting example for H synchronization pulses (for an NTSC 270,000 pixel CCD)
Name H synchronization pulse 1 H synchronization pulse 2 H synchronization pulse 3 H synchronization pulse 4 H synchronization pulse 5 H synchronization pulse 6 H synchronization pulse 7 H synchronization pulse 8 H synchronization pulse 9 Symbol H1 H2 H3 H4 H5 H6 H7 H8 H9 D10 D1 539 236 22 46 67 90 95 120 138 Notes Values with respect to the falling edge of HREFI. Values with respect to H synchronization pulses 1 and 2.
10 0001 1011 00 1110 1100 0001 0110 0010 1110 0100 0011 0101 1010 0101 1111 0111 1000 1000 1011
*
When a 410,000 pixel CCD is used, the following timings, which are related to the sensor clock and the sensor specifications, change. -- Memory R/W start/stop addresses -- BF, CBLK, CSYNC pulse timings -- Iris state data A13, H count 1 to 6
31
HD49801FB
* Notes on the Y/C digital interface
HD49801FB
-- Y is the post-gamma compensation output, and the color signal is the color difference signal output. -- The digital interface clock is proportional to the sensor clock frequency. It can handle 270,000 or 410,000 pixel sensors, and either the NTSC or PAL format. -- The upper 4 bits are added to the lower 4 bits, which are delayed by 1 clock cycle, and output.
Phase signal NRYBYO f's Clock DICK (R-Y)n (R-Y)n (B-Y)n (B-Y)n (R-Y)n (R-Y)n (B-Y)n (B-Y)n (R-Y)n (R-Y)n (B-Y)n (B-Y)n H L H L +1H +1L +1H +1L +2H +2L +2H +2L (R-Y)n' (R-Y)n' (B-Y)n' (B-Y)n' (R-Y)n' (R-Y)n' (B-Y)n' (B-Y)n' H L H L +1H +1L +1H +1L Ym Ym' Ym + 1 Ym + 2 Ym + 3 Ym + 4 Ym + 5 Ym + 6 Ym + 1' Ym + 2' Ym + 3' Ym + 4' Ym + 5' Ym + 6' fs: Sensor clock frequency L CPO1 to CPO4 CPI1 to CPI4 D1 to D4 (D1: LSB) H D5 to D8 (D8: MSB) (two's complement)
CPO1 to CPO4 CPI1 to CPI4 YPO1 to YPO8 YPI1 to YPI8
33
HD49801FB
* Notes on the Y/C digital interface
HD49801FB
-- Y is the post-gamma compensation output, and the color signal is the color difference signal output. -- The digital interface clock is proportional to the sensor clock frequency. It can handle 270,000 or 410,000 pixel sensors, and either the NTSC or PAL format. -- The upper 4 bits are added to the lower 4 bits, which are delayed by 1 clock cycle, and output.
Phase signal NRYBYO f's Clock DICK (R-Y)n (R-Y)n (B-Y)n (B-Y)n (R-Y)n (R-Y)n (B-Y)n (B-Y)n (R-Y)n (R-Y)n (B-Y)n (B-Y)n H L H L +1H +1L +1H +1L +2H +2L +2H +2L (R-Y)n' (R-Y)n' (B-Y)n' (B-Y)n' (R-Y)n' (R-Y)n' (B-Y)n' (B-Y)n' H L H L +1H +1L +1H +1L Ym Ym' Ym + 1 Ym + 2 Ym + 3 Ym + 4 Ym + 5 Ym + 6 Ym + 1' Ym + 2' Ym + 3' Ym + 4' Ym + 5' Ym + 6' fs: Sensor clock frequency L CPO1 to CPO4 CPI1 to CPI4 D1 to D4 (D1: LSB) H D5 to D8 (D8: MSB) (two's complement)
CPO1 to CPO4 CPI1 to CPI4 YPO1 to YPO8 YPI1 to YPI8
33
HD49801FB
SSG Internal Block Diagram
HD49801FB
The PLL format corresponding to the TG or TV formats used can be selected in the HD49801FB. * NTSC -- The H oscillator is unused (state data A16 PLLON = 0) -- When the PLL is applied to the sensor side TG:
FFSCO 13 14.31818 MHz 4 fsc osc 14 3 63 65 VRI HREFI SCKI
11 1/4
SCO
15 fsc (3.579545 MHz) H/V counter V.Reset FVO VDO TGSYNCO CHDO CBLKO fs system TG BFO CSYNCO IDO 7 6 96 97 4 8 5 9
fs
fs HD TG
V.Reset PLL VCO Phase comp.
34
HD49801FB
* NTSC -- The H oscillator is unused (state data A16 PLLON = 0) -- When the PLL is applied to the DSP side 4 fsc.
HD49801FB
FFSCO 13 14.31818 MHz 4 fsc osc 14 3 63 65 VRI HREFI SCKI
11 1/4
SCO
15 fsc (3.579545 MHz) H/V counter V.Reset FVO VDO TGSYNCO CHDO CBLKO fs system TG BFO CSYNCO IDO 7 6 96 97 4 8 5 9
fs
fs HD V.Reset
TG
Phase comp.
35
HD49801FB
* NTSC -- The H oscillator is used (state data A16 PLLON = 1) -- See the description of NTSC on pages 34 and 35 for sensor side TG.
HD49801FB
11 FFSCO SCO
15 fsc (3.579545 MHz) Phase comp. 1/161 PLLPO PLLNO 1 2 LPF
13 14.31818 MHz 4 fsc osc 14
1/4
1/184 FVO 7 6 96 97 4 8 5 9
99 4.090908 MHz 260 fH osc 100 3 63 VDD 65 VRI HREFI SCKI
1/2 H/V counter V.Reset
VDO TGSYNCO CHDO CBLKO
fs
fs system TG
BFO CSYNCO IDO
36
HD49801FB
* PAL/SECAM -- The H oscillator is used (state data A16 PLLON = 1) -- See the description of NTSC on pages 34 and 35 for sensor side TG.
HD49801FB
11 FFSCO SCP
15 fsc (4.43361875 MHz) Phase comp. 1/161 PLLPO PLLNO 1 2 LPF
13 17.734475 MHz 4 fsc osc 14
1/4
1/16 FVO 7 6 96 97 4 8 5 9
99 4.40625 MHz 282 fH osc 100 3 63 VDD 65 VRI HREFI SCKI
1/2 H/V counter V.Reset
VDO TGSYNCO CHDO CBLKO
fs
fs system TG
BFO CSYNCO IDO
37
38
(2) 4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 (3) 1 (3) 1 2 4 6 8 (4) 2 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
516 518 520 522 524 0
2f H
HD49801FB
FVO
NTSC Timing Chart
VDO
CHDO
TGSYNCO
HREFI
CBLKO*
BFO*
CSYNCO*
516 518 520 522 524 0
2f H
FVO
This figure shows the timing chart conforming to the NTSC TV format.
VDO
CHDO
TGSYNCO
HREFI
CBLKO*
BFO*
CSYNCO*
HD49801FB
Note: * The sensor clock (fs) system is set by state data A14.
HD49801FB
130f H 126 128 0 2 4 6 8 10 20 30 40 50 60 70 80 90 100 120
0.489 s 128 0 2 4 6
10.269 s 4.89 s 5 15 70 80
CHDO
2f H 5 15
H 5 10 70 75
TGSYNCO 5 60
EQ 70 125
SER
1H = 63.5558 s
HD49801FB
39
40
(4 4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 1) (1 1 2 4 6 8 2 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 2)
616 618 620 622 624 0
2f H
HD49801FB
FVO
VDO
CHDO
PAL/SECAM Timing Chart
TGSYNCO
HREFI
CBLKO*
BFO*
CSYNCO*
IDO
616 618 620 622 624 0
2f H
This figure shows the timing chart conforming to the PAL TV format.
FVO
VDO
CHDO
TGSYNCO
HREFI
CBLKO*
BFO*
CSYNCO*
IDO
HD49801FB
Note: * The sensor clock (fs) system is set by state data A14.
(2 2 616 618 620 622 624 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 3
3)
2f H
HD49801FB
FVO
VDO
CHDO
TGSYNCO
HREFI
CBLKO*
BFO*
CSYNCO*
IDO (3 3 616 618 620 622 624 0 2 4 6 8 4 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 4)
2f H
FVO
VDO
CHDO
TGSYNCO
HREFI
CBLKO*
BFO*
CSYNCO*
IDO
HD49801FB
41
Note: * The sensor clock (fs) system is set by state data A14.
42
0.4539 s 20 30 40 50 60 70 80 90 100 110 120 130 140 0 2 4 10.439 s 23 4.539 s 6 16 76 86 6 16 6 11 76 81 6 65 76 136 1H = 64 s
HD49801FB
141f H
140 0 2 4 6 8 10
0
CHDO
2f H
H
TGSYNCO
EQ
SER
HD49801FB
HD49801FB
* Odd/even determination signal This is determined by latching CHD on the falling edge of FV.
HD49801FB
FV
FV
CHD (odd)
CHD (even)
*
IDO for PAL/SECAM The change point agrees with the falling edge of C.SYNC.
IDO
In PAL mode: ID = high: Modulates at R-Y + polarity ID = low: Modulates at R-Y - polarity In SECAM mode: ID = high: B-Y output ID = low: R-Y output The (R-Y) polarity inversion in PAL mode is performed in the encoder that follows the digital interface.
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